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integrated silicon solution, inc. ? 1-800-379-4774 1 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 128k-bit/ 256k-bit spi serial electrically erasable prom features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? low power cmos ? active current less than 3.0 ma (2.5v) ? standby current less than 20 a (2.5v) ? low-voltage operation ? vcc = 1.8v to 5.5v ? block write protection ? protect 1/4, 1/2, or entire array ? 64 byte page write mode ? partial page writes allowed ? 2.1 mhz clock rate (5v) ? self timed write cycles ? 5ms max @ 2.5v ? high-reliability ? endurance: 1,000,000 cycles per byte ? data retention: 100 years ? 8-pin jedec soic, 8-pin eiaj soic, and 8-pin pdip packages available ? industrial and automotive temperature ranges ? lead-free available advanced information july 2006 description the is25c128 and IS25C256 are electrically erasable prom devices that use the serial peripheral interface (spi) for communications. the is25c128 is 128kbit (16k x 8) and the IS25C256 is 256kbit (32k x 8). the is25c128/256 eeproms are offered in a wide operating voltage range of 1.8v to 5.5v for compatibility with most application voltages. issi designed the is25c128/256 to be an efficient spi eeprom solution. the devices are packaged in 8-pin jedec soic, 8-pin eiaj soic, and 8-pin pdip. the functional features of the is25c128/256 allow them to be among the most advanced serial non-volatile memories available. each device has a chip-select ( cs ) pin, and a 3-wire interface of serial data in (si), serial data out (so), and serial clock (sck). while the 3-wire interface of the is25c128/256 provides for high-speed access, a hold pin allows the memories to ignore the interface in a suspended state; later the hold pin re-activates communication without re- initializing the serial sequence. a status register facilitates a flexible write protection mechanism, and a device-ready bit ( rdy ).
2 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? write protect ( wp wp wp wp wp ): the purpose of this input signal is to initiate hardware write protection mode. this mode prevents the block protection bits and the wpen bit in the status register from being altered. to cause hardware write protection, wp must be low at the same time wpen is 1. wp may be hardwired to vcc or gnd. hold ( hold hold hold hold hold ): this input signal is used to suspend the device in the middle of a serial sequence and temporarily ignore further communication on the bus (si, so, sck). together with chip select, the hold signal allows multiple slaves to share the bus. the hold signal transitions must occur only when sck is low, and be held stable during sck transitions. (see figure 8 for hold timing) to disable this feature, hold may be hardwired to vcc. pin descriptions cs chip select sck serial data clock si serial data input so serial data output gnd ground v cc power wp write protect hold suspends serial input pin descriptions serial clock (sck): this timing signal provides syn- chronization between the microcontroller and is25c128/ 256. op-codes, byte addresses, and data are latched on si with a rising edge of the sck. data on so is refreshed on the falling edge of sck for spi modes (0,0) and (1,1). serial data input (si): this is the input pin for all data that the is25c128/256 is required to receive. serial data output (so): this is the output pin for all data transmitted from the is25c128/256. pin configuration 8-pin dip and soic chip select ( cs cs cs cs cs ): the cs pin activates the device. upon power-up, cs should follow vcc. when the device is to be enabled for instruction input, the signal requires a high-to-low transition. while cs is stable low, the master and slave will communicate via sck, si, and so signals. upon completion of communication, cs must be driven high. at this moment, the slave device may start its internal write cycle. when cs is high, the device enters a power-saving standby mode, unless an internal write operation is underway. during this mode, the so pin becomes high impedance. 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si
integrated silicon solution, inc. ? 1-800-379-4774 3 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? serial interface description master: the device that provides a clock signal. slave: the is25c128/256 is a slave because the clock signal is an input. transmitter/receiver: the is25c128/256 has both data input (si) and data output (so). msb: the most significant bit. it is always the first bit transmitted or received. op-code: the first byte transmitted to the slave follow- ing cs transition to low. if the op-code is a valid member of the is25c128/256 instruction set (table 3), then it is decoded appropriately. if the op-code is not valid, and the so pin remains in high impedance. block diagram status register 16k x 8/32k x 8 memory array hold cs wp clock so output buffer sck si data register mode decode logic gnd vcc address decoder
4 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? status register table 1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 wpen x x x bp1 bp0 wen rdy the status register contains 8-bits for write protection control and write status. (see table 1). it is the only region of memory other than the main array that is accessible by the user. the status register is read-only if either: a) hardware write protection is enabled or b) wen is set to 0. if neither is true, it can be modified by a valid instruction. ready ( rdy rdy rdy rdy rdy ), bit 0: when rdy = 1, it indicates that the device is busy with a write cycle. rdy = 0 indi- cates that the device is ready for an instruction. if rdy = 1, the only command that will be handled by the device is read status register. don?t care, bits 4-6: each of these bits can receive either 0 or 1, but values will not be retained. when these bits are read from the register, they are always 0. write protect enable (wpen), bit 7: this bit can be used in conjunction with wp pin to enable hardware write protection, which causes the status register to be read-only. the memory array is not protected by this mode. hardware write protection requires that wp = 0 and wpen = 1; it is disabled otherwise. note: wpen cannot be changed from 1 to 0 if the wp pin is already set to low. (see table 4 for data protection relationship) notes: 1. x = don't care bit. 2. during internal write cycles, bits 0 to 7 are temporarily 1's. block protect (bp1, bp0), bits 2-3: together, these bits represent one of four block protection configurations implemented for the memory array. (see table 2 for details.) bp0 and bp1 are non-volatile cells similar to regular array cells, and factory programmed to 0. the block of memory defined by these bits is always protected, regardless of the setting of wpen, wp , or wen. table 2. block protection status register bits array addresses protected level bp1 bp0 is25c128 IS25C256 0 0 0 none none 1(1/4) 0 1 3000h 6000h -3fffh -7fffh 2(1/2) 1 0 2000h 4000h -3fffh -7fffh 3(all) 1 1 0000h 0000h -3fffh -7fffh write enable (wen), bit 1: this bit represents the status of device write protection. if wen = 0, the status register and the entire array is protected from modifica- tion, regardless of the setting of wpen, wp pin, or block protection. the only way to set wen to 1 is via the write enable command (wren). wen is reset to 0 upon power-up.
integrated silicon solution, inc. ? 1-800-379-4774 5 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? write enable (wren) when vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. upon completion of write disable (wrdi), write status register (wrsr), or write data to array (write), the device resets the wen bit in the status register to 0. prior to any data modification, a wren instruction is necessary to set wen to 1. (see figure 2 for timing). write disable (wrdi) the device can be completely protected from modifica- tion by resetting wen to 0 through the wrdi instruc- tion. (see figure 3 for timing). read status register (rdsr) the read status instruction tells the user the status of write protect enable, the block protection setting (see table 2), the write enable state, and the rdy status. rdsr is the only instruction accepted when a write cycle is underway. it is recommended that the status of write enable and rdy be checked, especially prior to an attempted modification of data. the 8 bits of the status register can be repeatedly output on so after the initial op-code. (see figure 4 for timing). table 3. instruction set name op-code operation address data(si) data (so) wren 0000 x110 set write enable latch - -- wrdi 0000 x100 reset write enable latch - - - rdsr 0000 x101 read status register - - d7-d0,... wrsr 0000 x001 write status register - d7-d0 - read 0000 x011 read data from array a15-a0 - d7-d0,... write 0000 x010 write data to array a15-a0 d7-d0,... - device operation t he operations of the is25c128/256 are controlled by a set of instructions that are clocked-in serially si pin. (see table 3). to begin an instruction, the chip select ( cs ) should be dropped low. subsequently, each low-to-high transition of the clock (sk) will latch a stable value on the si pin. after the 8-bit op-code, it may be appropriate to continue to input an address or data to si, or to output data from so. during data output, values appear on the falling edge of sk. all bits are transferred with msb first. upon the last bit of communication, but prior to any following low- to-high transition of sk, cs should be raised high to end the transaction. the device then would enter standby mode if no internal programming were underway. notes: 1. x = don?t care bit. for consistency, it is best to use ?0?. 2. some address bits are don?t care. see table 5. 3. if the bits clocked-in for an op-code are invalid, so remains high impedance, and upon cs going high there is no affect. a valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or status register to be ignored.
6 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? table 5. address key name is25c128 IS25C256 a n a 13- a 0 a 14- a 0 don't a 15- a 14 a 15 care bits write status register (wrsr) this instruction lets the user choose a block protection setting, and set or reset the wpen bit. the values of the other data bits incorporated into wrsr can be 0 or 1, and are not stored in the status register. wrsr will be ignored unless both the following are true: a) wen = 1, due to a prior wren instruction; and b) hardware write protection is not enabled. (see table 4 for de- tails). except for the rdy status, the values in the status register remain unchanged until the moment when the write cycle is complete and the register is updated. note: wpen can be changed from 1 to 0 only if wp is already set high. once completed, wen is reset for complete chip write protection. (see figure 5 for timing). read data (read) this instruction begins with the op-code and the 16-bit address, and causes the selected data byte to be shifted out on so. following this first data byte, addi- tional sequential bytes are output. if the data byte in the highest address is output, the address rolls-over to the lowest address in the array, and the output could loop indefinitely. at any time, a rising cs signal completes the operation. (see figure 6 for timing). write data (write) the write instruction begins with the op-code, the 16- bit address of the first byte to be modified, and the first data byte. additional data bytes may be written sequen- tially to the array after the first byte. each write instruction can affect the contents of a 64 byte page, but no more. the page begins at address xxxxxxxx xx000000, and ends with xxxxxxxx xx111111. if the last byte of the page is input, the address rolls over to the beginning of the same page. more than 64 data bytes can be input during the same instruction, but upon a completed write cycle, a page would only contain the last 64 bytes. the region of the array defined within block protection cannot be modified as long as that block configuration is selected. the region of the array outside the block protection can only be modified if write enable (wen) is set to 1. therefore, it may be necessary that a wren instruction occur prior to write. hardware write protection has no affect on the memory array. once write is completed, wen is reset for complete chip write protection. (see figure 7 for timing). table 4. write protection wpen wp wp wp wp wp hardware write wen inside block outside block status register protection (wpen, bp1, bp0) 0 x not enabled 0 read-only read-only read-only 0 x not enabled 1 read-only unprotected unprotected 1 0 enabled 0 read-only read-only read-only 1 0 enabled 1 read-only unprotected read-only x 1 not enabled 0 read-only read-only read-only x 1 not enabled 1 read-only unprotected unprotected note: x = don't care bit.
integrated silicon solution, inc. ? 1-800-379-4774 7 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? absolute maximum ratings (1) symbol parameter value unit v s supply voltage -0.5 to + 6.5 v v p voltage on any pin ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (IS25C256-2 and is25c128-2) range ambient temperature v cc industrial ?40c to +85c 1.8v to 5.5v note: 1. issi offers industrial grade for commercial applications (0 o c to +70 o c). capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 5.0v. operating range (IS25C256-3 and is25c128-3) range ambient temperature v cc automotive ?40c to +125c 2.5v to 5.5v
8 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? dc electrical characteristics t a = ?40c to +85c for industrial, t a = ?40c to +125c for automotive. symbol parameter test conditions min. max. unit v ol 1 output low voltage v cc = 5v, i ol = 3 ma ? 0.4 v v ol 2 output low voltage v cc = 2.5v, i ol = 1.5 ma ? 0.4 v v ol 3 output low voltage v cc = 1.8v, i ol = 0.15 ma ? 0.2 v v o h1 output high voltage v cc = 5v, i oh = -3 ma 0.8 x v cc ?v v o h2 output high voltage v cc = 2.5v, i oh = -0.4ma 0.8 x v cc ?v v o h3 output high voltage v cc = 1.8v, i oh = -0.1ma 0.8 x v cc ?v v ih input high voltage 0.7 x v cc v cc + 1 v v il input low voltage -1.0 0.3 x v cc v i li input leakage current v in = 0v to v cc -3 3 a i lo output leakage current v out = 0v to v cc , cs = v cc -3 3 a power supply characteristics t a = ?40c to +85c for industrial. symbol parameter test conditions min. max. unit i cc 1 vcc operating current read/write at 2.1 mhz (vcc = 5v) ? 5.0 ma i cc 2 vcc operating current read/write at 2.1 mhz (vcc = 2.5v) ? 3.0 ma i cc 3 vcc operating current read/write at 500 khz (vcc = 1.8v) ? 2.0 ma i sb 1 standby current vcc = 5.0v, v in = v cc or gnd ? 25 a cs = vcc i sb 2 standby current vcc = 2.5v, v in = v cc or gnd ? 20 a cs = vcc i sb 3 standby current vcc = 1.8v, v in = v cc or gnd ? 15 a cs = vcc power supply characteristics t a = ?40c to +125c for automotive. symbol parameter test conditions min. max. unit i cc 1 vcc operating current read/write at 2.1 mhz (vcc = 5v) ? 6.0 ma i cc 2 vcc operating current read/write at 2.1 mhz (vcc = 2.5v) ? 3.0 ma i sb 1 standby current vcc = 5.0v, v in = v cc or gnd ? 30 a cs = vcc i sb 2 standby current vcc =2.5v, v in = v cc or gnd ? 20 a cs = vcc
integrated silicon solution, inc. ? 1-800-379-4774 9 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? ac characteristics t a = ?40c to +85c for industrial. 1.8v vcc < 2.5v 2.5v vcc 5.5v symbol parameter min max min max units f sck sck clock frequency 0 0.5 0 2.1 mhz t ri input rise time ? 2 ? 2 s t fi input fall time ? 2 ? 2 s t wh sck high time 800 ? 200 ? ns t wl sck low time 800 ? 200 ? ns t cs cs high time 200 ? 100 ? ns t css cs setup time 200 ? 90 ? ns t csh cs hold time 200 ? 90 ? ns t su data in setup time 40 ? 20 ? ns t h data in hold time 50 ? 30 ? ns t hd hold setup time 100 ? 50 ? ns t cd hold hold time 100 ? 50 ? ns t v output valid 0 150 0 60 ns t ho output hold time 0 ? 0 ? ns t lz hold to output low z 0 100 0 50 ns t hz hold to output high z ? 250 ? 100 ns t dis output disable time ? 250 ? 100 ns t wc write cycle time ? 10 ? 5 ms c l = 100pf
10 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? ac characteristics t a = ?40c to +125c for automotive. 2.5v vcc 5.5v symbol parameter min max units f sck sck clock frequency 0 2.1 mhz t ri input rise time ? 2 s t fi input fall time ? 2 s t wh sck high time 200 ? ns t wl sck low time 200 ? ns t cs cs high time 100 ? ns t css cs setup time 90 ? ns t csh cs hold time 90 ? ns t su data in setup time 20 ? ns t h data in hold time 30 ? ns t hd hold setup time 50 ? ns t cd hold hold time 50 ? ns t v output valid 0 60 ns t ho output hold time 0 ? ns t lz hold to output low z 0 50 ns t hz hold to output high z ? 100 ns t dis output disable time ? 100 ns t wc write cycle time ? 5 ms c l = 100pf
integrated silicon solution, inc. ? 1-800-379-4774 11 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? timing diagrams figure 3. wrdi timing figure 2. wren timing figure 1. synchronous data timing cs sk d in d out v ih v il v ih v il v ih v il v oh v ol valid in high-z high-z t css t wh t wl t h t su t cs t csh t v t ho t dis high-z wren op-code cs sk d in d out high-z wrdi op-code cs sk d in d out
12 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? figure 6. read timing figure 5. wrsr timing figure 4. rdsr timing cs sk din dout instruction 7 6 5 4 3 2 1 0 data out 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sk din dout instruction byte address 7 6 5 4 3 2 1 0 data out cs sk din dout instruction 7 6 5 4 3 2 1 0 data i n
integrated silicon solution, inc. ? 1-800-379-4774 13 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? figure 8. hold hold hold hold hold timing figure 7. write timing 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sk din dout instruction byte address data in cs sck hold d out t cd t hd t hz t lz t hd t cd
14 integrated silicon solution, inc. ? 1-800-379-4774 advanced information rev. 00e 06/13/06 is25c128 IS25C256 issi ? ordering information industrial range: ?40c to +85c voltage range part number package 1.8v is25c128-2gi sm all outline (jedec std) to 5.5v is25c128-2gli small outline (jedec std), lead-free is25c128-2pi 300-mil plastic dip is25c128-2pli 300-mil plastic dip, lead-free is25c128-2wi small outline (eiaj std) is25c128-2wli sm all outline (eiaj std), lead-free 1.8v IS25C256-2gi sm all outline (jedec std) to 5.5v IS25C256-2gli small outline (jedec std), lead-free IS25C256-2pi 300-mil plastic dip IS25C256-2pli 300-mil plastic dip, lead-free IS25C256-2wi small outline (eiaj std) IS25C256-2wli sm all outline (eiaj std), lead-free ordering information automotive range: ?40c to +125c voltage range part number package 2.5v is25c128-3ga3 sm all outline (jedec std) to 5.5v is25c128-3gla3 small outline (jedec std), lead-free is25c128-3pa3 300-mil plastic dip is25c128-3pla3 300-mil plastic dip, lead-free is25c128-3wa3 small outline (eiaj std) is25c128-3wla3 sm all outline (eiaj std), lead-free 2.5v IS25C256-3ga3 sm all outline (jedec std) to 5.5v IS25C256-3gla3 small outline (jedec std), lead-free IS25C256-3pa3 300-mil plastic dip IS25C256-3pla3 300-mil plastic dip, lead-free IS25C256-3wa3 small outline (eiaj std) IS25C256-3wla3 sm all outline (eiaj std), lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/14/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 300-mil plastic dip package code: n,p a d 1 b n seating plane c a1 e a l e b1 s e1 e s for 32-pin only b2 millimeters inches sym. min. max. min. max. n0. leads 8 a 3.68 4.57 0.145 0.180 a1 0.38 ? 0.015 ? b 0.36 0.56 0.014 0.022 b1 1.14 1.52 0.045 0.060 b2 0.81 1.17 0.032 0.046 c 0.20 0.33 0.008 0.013 d 9.12 9.53 0.359 0.375 e 7.62 8.26 0.300 0.325 e1 6.20 6.60 0.244 0.260 e a 8.13 9.65 0.320 0.380 e 2.54 bsc 0.100 bsc l 3.18 ? 0.125 ? s 0.64 0.762 0.025 0.030 notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 2 rev. c 10/03/01 150-mil plastic sop package code: g, gr d seating plane b e c 1 n e a1 a h l notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 150-mil plastic sop (g, gr) symbol min max min max ref. std. inches mm no. leads 8 8 a ? 0.068 ? 1.73 a1 0.004 0.009 0.1 0.23 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.18 0.25 d 0.189 0.197 4.8 5 e 0.150 0.157 3.81 3.99 h 0.228 0.245 5.79 6.22 e 0.050 bsc 1.27 bsc l 0.020 0.035 0.51 0.89
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 2 rev. a 10/20/05 200-mil plastic sop package code: w notes: 1. controlling dimension: mm, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 200-mil plastic sop (w) symbol min max min max ref. std. inches mm no. leads 8 8 a ? 0.085 ? 2.16 a1 0.004 0.009 0.10 0.23 b 0.014 0.018 0.35 0.45 c 0.006 0.014 0.15 0.35 d 0.203 0.211 5.15 5.35 e 0.204 0.213 5.18 5.40 h 0.303 0.325 7.70 8.26 e 0.050 bsc 1.27 bsc l 0.020 0.033 0.51 0.85 d seating plane b e c 1 n e a1 a h l

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